On the Use of Microarchitecture-Driven Dynamic Voltage Scaling

This paper proposes microarchitecture-driven dynamic voltage scaling as a viable solution to power efficient architectures, with little or no performance penalty. The run-time behavior exhibited by common applications, with active periods, alternated with stall periods due to cache misses, is exploited to reduce the dynamic component of power consumption via selective voltage scaling. As it is shown by experimental results, up to 20% reduction in total energy consumption, 22% in average power and 14% in peak power have been achieved with less than 6% penalty in performance. The study shows that microarchitecture-driven dynamic voltage scaling can become an effective tool for energy reduction in high-performance processors.